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Altera_Forum
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13 years ago

How to avoid glitch in combinational logic?

In FPGA design, when we design a combinational logic, there may appear glitch since the time property is not ideal in each components. And sometime glitch may cause problem. But how can avoid glitc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I can't figure out why a single flip-flip (register) to eliminate glitches is not sufficient but two series connected flip-flop will works. If the first ff is violated by metastable，how can the second ff get the right state?

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It cannot guarantee it, it just reduces the probability that the output of the second register will be metastable. If you test your hardware and find metastability issues, then you can increase the number of registers in the synchronizer chain.

Cheers,

Dave