How to avoid glitch in combinational logic?

You have two glitch cases;

1) Enable.

If the enable signal routes to the d input of a register, then TimeQuest will indicate whether the combinatorial delay along the path of a and b, and the combinatorial signal a&&b is small enough that it does not violate the register timing.

2) Reset.

If the reset signal routes to the asynchronous reset port on a register, then you must synchronize that signal to the clock used by the register to ensure that the reset recovery/removal timing of the register is met.

In the case of your reset logic input signals coming from arbitrary sources, a single flip-flip (register) to eliminate glitches is not sufficient, you need to use at least two layers of registers, and the clock input to those registers needs to be the same clock as used by the registers it is resetting. If you have multiple clock domains, then you need multiple reset synchronizers.

Cheers,

Dave