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Altera_Forum's avatar
Altera_Forum
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10 years ago

How to assign an entity located within a generate statement to a logiclock region?

Dear all

I'm trying to assign an entity, which is inside a (VHDL) generate statement, to a logiclock region:

set_instance_assignment -name LL_MEMBER_OF MEMIFLL -to "MEMIF:\B0:MIF|MEMRD:MRD" -section_id MEMIFLL

However there seems to be something wrong with the assignment, as it is always either cleared out of the *.qsf fileby Quartus. A second assignment

set_instance_assignment -name LL_MEMBER_OF MEMIFLL -to "SEQLD:SLD" -section_id MEMIFLL

does work a expected, it is assigned to and placed within the region.

It looks to me that the tool is not able to cope with the "\" character. So how is it done (a wildcard "*" at the position didn't work either...)?

Thanks!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    When I had to mess about with regions, it was much easier doing it in the floorplanner. You could find your entity in the noise finder, which will give you the correct path. Then you can just copy, paste or modify the path

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I assume you had the node finder in mind. Not my favourite to click through the GUI each time.

    However, I found the solution in meantime. In *.qsf (otherwise than in *.sdc :-( ) a second "\" character is required to announce the special one, like:

    set_instance_assignment -name LL_MEMBER_OF MEMIFLL -to "MEMIF:\\B0:MIF|MEMRD:MRD" -section_id MEMIFLL