Contributor
Super ContributorIf the assignments were ignored, chances are the Fitter was not able to find a placement solution for your clock network that would let it use the regional clock networks.
When you say your PLL clock loading is "light", what do you mean? Why do you think you need to do this? Are you not meeting timing/performance?
ContributorHi sstrell
0.0, OK, I understand it that tool can't meet assignment. So, tool ignore it. And I said that PLL clock loading is "light" because fan-out are very less as follows picture.
My FPGA usage is to do SoC verification. So, I really want to assign those PLL clock to use regional clock because other clocks need to use global clock network to get better performance.
In critical cases, the design get a little timing violation, but it's OK because FPGA can work well in the normal environment.
Although FPGA can work well, I want to clear the timing violation to make sure the system is robust.
Does those ignored assignments are mean that if those PLL clocks use regional clocks, performance will get down?
Thank you, sstrell, very much.
