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jrrguzman
Occasional Contributor
Occasional ContributorHow to assign a dual-region clock network in assignment editor?
Hi, I got Cyclone V SoC design with a parallel port split into two different regional clock networks. This port is driven by a PLL clock and I would like to force the PLL to use a regional clock net...
jrrguzmanOccasional Contributor
Occasional ContributorHi,
It's not an error. The fitter does not recognize the assignment and it does not apply it.
Anyway, I've managed to achieve the desired effect by populating the clock buffer myself and use a "~_Duplicate" modified at the sd1 component to force a dual region clock network. Anyway, I would have liked to be able to do this automatically without using a dedicated clock buffer.
Cheers.
