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I don't think you can simulate this with ModelSim, at least not when performing an RTL level simulation.
The only way that I can see to do that, would be to add in the HDL code, an async clear to all the registers you are using. Take this async clr signal to the top level, and makes your testbench assert it as the device-wide reset. If you are already using some other async reset signal, combine both the local and wide reset as needed.
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hi,vjAlter!
i think i find some way to do this simulation,see the following link:
http://www.altera.com.cn/support/software/nativelink/quartus2/eda_pro_advanced_options.html and see 10.b, if you enable the option
bring out device-wide set/reset signals as ports, when you
start test bench template writer,the generated test bench will add the "devclrn","devpor" in the test bench port map ,like following:
frequency_div i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.clk_100k(clk_100k),
.rst_n(rst_n),
.devpor(devpor_tst),
.devclrn(devclrn_tst)
);
// devpor
initial
begin
devpor_tst = 1'b1;
end
// devclrn
initial
begin
devclrn_tst = 1'b1;
end
i tried set the devclrn_tst = 1'b0, all of the registers will be 0, no matter i tried to set it to 1.
but there is no "devoe" signal in the port map, i didn't know why?
Honored Contributor
