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Altera_Forum's avatar
Altera_Forum
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12 years ago

How should I write Verilog to describe DDR?

I have a design, which I need make the data is launched by double data rate (DDR). In this case, should I write the Verilog like this ? : always @(posedge clk or negedge clk) begin output <...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Just to clarify, one can describe synthesizable DDR I/O in Verilog but, as FvM said, Quartus won't infer it and won't use the DDR I/O logic embedded in the I/O elements.

So, you should use the altddio_out megafunction.