How often do you use Incremental Compilation?

I like Rysc's explanation. I tried a couple of times to venture down the path of IC. My intention was to lock down the large megafunctions such DDR controllers, xaui interfaces, qdr interfaces, etc. and then pass around the project to other team members. But that did not pan out very well. Generally, it was Altera's megafunction's that would have problems with this. E.g. the timing scripts would have problems, etc.

So now we just run a full compile. Using verilog macros we simply limit the functionality and therefore the module instances during development. Subsequently, we would run the full design. I used to think that we needed to develop better rules to write the logic but Rysc's post tells me that it not be all that beneficial.