How is memory synthesized by quartus ii ?

From the examples which you have shown, it seems that the tool will synthesize the code by using RAM blocks if I write something like:

module ram_single(q, a, d, we, clk); output[7:0] q; input [7:0] d; input [6:0] a; input we, clk; reg [7:0] mem [127:0]; always @(posedge clk) begin if (we) mem[a] <= d; q <= mem[a]; endendmodule

And If I write something like

reg [63:0] mem[4095:0];

The tool will be converting this into logic elements. Is this correct??