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gyuunyuu's avatar
gyuunyuu
Icon for Contributor rankContributor
5 years ago
Solved

How does Quartus know what is voltage on each FPGA I/O bank?

It is possible to connect different voltages to each bank of an FPGA. The I/O standard of the pins on the FPGA relies on what bank voltage has been connected to it. Now my questions are: 1. How d...
  • GLees's avatar
    GLees
    5 years ago

    To New Contributor I,

    In the Pin Planner you specify what voltage goes to each I/O bank. This is done on a pin-by-pin basis. It will give you a (compilation) error if you specify pins with two different voltages on the same bank. It's up to you to connect the correct voltage to each I/O bank on your circuit board.

gyuunyuu's avatar
gyuunyuu
Icon for Contributor rankContributor
5 years ago

Please check the attached image. It shows the available options for the pin I/O standards. The options are all over the place.

If Quartus knew that my I/O bank was lets say at 3.3V, it won't show me all those 1.0V and 2.5V options in the drop down menu. Do you understand my question now?

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

If you select an invalid I/O standard voltage for your device, you'll get an error during compilation.

  • gyuunyuu's avatar
    gyuunyuu
    Icon for Contributor rankContributor
    5 years ago

    How does it know if it is invalid? I never told it what voltage supply I connected to the bank to begin with.

    There is no option where we can specify what voltage supply is connected per bank on the FPGA.

    None.

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hello,

      It will be invalid if your setting does not meet the specifications of the device. We have a lot of tutorial videos about using Quartus on our Intel FPGA Youtube channel. Here is the video about Chip Planner in Quartus Prime Pro Software: https://www.youtube.com/watch?v=Bt-yDRReKZw

      Thanks

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hello,

      Is all of your questions addressed? I will need to close this case if there is no update from you in 3 days.

      Thanks.

      • gyuunyuu's avatar
        gyuunyuu
        Icon for Contributor rankContributor
        5 years ago

        Please clarify what part of the video are referring to in your previous message. Also, is a valid input simply what the FPGA pins can handle or what is actually a function of the bank voltage? If the I/O bank is supplied by 3.3V supply then the pin planner should not even show the option to specify a 1.8V I/O standard for any pin on it. I don't think this is how pin planner works.