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RKapi's avatar
RKapi
Icon for New Contributor rankNew Contributor
7 years ago

how do you map an array to a std_logic_vector?

For eg: I have an array - type REG_TYPE is array (0 to FIR_ORDER-1) of signed (DATA_WIDTH+COEFF_WIDTH-1 downto 0) and another signal X: REG_TYPE. As per the need of the requirement, i would be cal...
mfro's avatar
mfro
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

>> This is showing an error.

What error?

It would be a lot easier to help you if you would show your code.