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That's fascinating. Apart from the voltage level difference, there shouldn't be any algorithmic or (conceptual) wiring differences between your design and mine.
Would you mind describing the programming sequence, any non-default device settings you may be using in Quartus, and perhaps a screen grab of the relevant bit of the schematic?
Then maybe we can get to the bottom of this issue and save everyone having to buy over priced EPCQ chips in future.
Thank you
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For the ARRIA10 :
1 - I configure the FPGA with a design includng with an embedded "Serial Flash Controller"
2 - Once this is done, you should be able to detect the JTAG chain and then appear the ARRIA10 + EPCQL-512 in the Programmer
3 - Program the FLASH with the .jic file (Disable EPCS ID checked, Disable CONF_DONE checked) through the programmer : Quartus read the ID=0x20 (capacity of the FLASH=512M)
I will try to attach a screenshot but I don' know how to do that for the moment....
Honored Contributor
