How do I split a bus into individual signal lines?

It does seem that a lot of people are going HDL.

I like schematic design because its easy for me to debug. I can just look at it and tell what its doing and what's wrong. I'm sure other people can do the same with HDL, but not me. I know HDL has several advantages, but one thing I did notice is that the HDL version of my project (done by others) took about 4X as many LE's as my schematic version did. The schematic version consisted entirely of logic primitives and TTL blocks so I didn't do any intensive optimizing.

That said, my next task is to figure out how to import HDL blocks into a schematic. Some of the Altera library components are HDL blocks so I know it can be done. I am thinking it is similar to the way its done with schematic blocks, but we'll see.