How do I handle fitter generated differential complement pins in the VHDL netlist?

Hi,

I am trying to modify an existing VHDL FPGA design (CycloneIII EP3C120F780C8) using Quartus II 11.0SP1 Web edition. I am having trouble with the simulation netlist for some LVDS differential outputs. For example:

1. In the VHDL entity:

sync_dac : out std_logic;

2. In the qsf file:

set_instance_assignment -name IO_STANDARD LVDS -to sync_dac

set_location_assignment PIN_V4 -to sync_dac

The input entity does not include the complement pin at V3. The fitter generates the complement pin:

Warning: Pin "sync_dac" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "sync_dac(n)"

The EDA netlist writer generates an entity with:

\sync_dac(n)\ : OUT std_logic;

Unfortunately, this entity is different to the original, but is given the

same name. If I turn off entity generation the netlist architecture includes a reference to an undefined signal:

\sync_dac(n)\ <= \ww_sync_dac(n)\;

I tried to tell the fitter the names of a differential pair this way:

Entity:

sync_dac : buffer std_logic;

sync_dac_n : out std_logic;

Arch:

sync_dac_n <= not sync_dac;

Attributes:

attribute altera_chip_pin_lc : string;

attribute altera_chip_pin_lc of sync_dac : signal is "V4";

attribute altera_chip_pin_lc of sync_dac_n : signal is "V3";

attribute altera_attribute : string;

attribute altera_attribute of sync_dac : signal is "-name IO_STANDARD LVDS";

Unfortunately, the fitter complains that the V3 pin is already assigned to \sync_dac(n)

Is there a VHDL altera_attribute that I can use to tell the fitter that a pin is part of a differential pair?

At present I am editing the simulation netlist by hand.

Thanks in advance.