How do I get SignalTap analyzer to stop calculating a different CRC to my FPGA file when I do a simple trigger condition change?

What version of Quartus that you had used? There are some workaround for older version of Quartus if you face this error:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd03272011_510.html

Also, can you put a screenshot here so that we can see what is missing in your signal tap? Yes, changing the trigger condition does not require you to full recompile of the design.

One things to note that, it is always advise that you have make your timing close before doing the hardware test. Had you make sure that your timing sdc was written correctly and the timing close?