How constraint the output delay from the different clock edge to the same pad?

As discussed in your other post, the clocks are first set up using create_generated_clock constraints. If you are saying that these generated clocks are output clocks that are used by external devices, then you need additional generated clock constraints to put these clocks at output ports of the device. Then you create your set_output_delay constraints with the -clock option pointing to these generated clocks. You also need the correct calculated values for the -max and -min output delay and false path constraints for the clock paths so they are not analyzed as data. Essentially, you're created a source synchronous output. See the online training for the details of what you probably need and adjust accordingly:

https://learning.intel.com/developer/learn/course/external/view/elearning/168/constraining-source-synchronous-interfaces