Forum Discussion
Hi,
From your code, the pins required are 960+16 = 976 pins. Clearly it cannot fit into a device with 360 pins only. The change to the code is totally dependent on the user application. What is required to be done with the input pins and how the outputs are required to be driven and how many, totally user decision.
We cannot directly suggest you the changes to be done. You got to discuss this with your project lead.
One way would be probably to get these 960 inputs through a processor register interface. This is just a personal suggestion.
Recommend you to subscribe to Intel FPGA YouTube channel for accessing various training videos.
Putting some basic videos for reference:
Verilog HDL Basics: https://www.youtube.com/watch?v=PJGvZSlsLKs
FPGA Design: https://www.youtube.com/watch?v=0Ho4rDswOeE&list=PL0pU5hg9yniZ2ka-XBXROXNR0pAEAEFCB
Basics of Programmable Logic: https://www.youtube.com/watch?v=jbOjWp4C3V4
How to Begin a Simple FPGA Design: https://www.youtube.com/watch?v=bwoyQ_RnaiA
Regards