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Altera_Forum's avatar
Altera_Forum
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15 years ago

HOLD timing violation

I am using timequest and getting a hold timing violation. the launch clock is a 10MHz clock generated from a PLL. the latch clock is 50MHz (from which the 10MHz is derived). my logic is doing an edge detection on the "from" signal in the "to" domain. in other words, i am using the 50MHz clock to edge detect on a 10MHz signal. I do not understand why there is a hold violation. any suggestions?

thanks

kevin

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You need to use synchronizer from 10 MHz to 50 MHz. Also, this is a flase path.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    why would it be a false path? the 10MHZ clock is generated from the 50MHz clock with a PLL? the clocks are related.

    for synchronization, i do an edge detect with the 50MHz clock on the 10MHz signal. this should be just fine. it's like sampling an asynchronous input. we do it all the time.