Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorhold timing and clock frequency considerations
hello all, two questions for the experts: 1. why hold time is not frequency depended? 2. will it be reasonable to assume that design that fits timing requirements with 100MHz clock fr...
Altera_ForumHonored Contributor
Honored Contributorthanks to both of you.
can you please elaborate about your answer to my second question? why it is ok to define the main clock of the design, lets say 100MHz, but actually inject to the fpga 80MHz clock?
