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Altera_Forum's avatar
Altera_Forum
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8 years ago

hold timing and clock frequency considerations

hello all, two questions for the experts: 1. why hold time is not frequency depended? 2. will it be reasonable to assume that design that fits timing requirements with 100MHz clock fr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

thanks to both of you.

can you please elaborate about your answer to my second question?

why it is ok to define the main clock of the design, lets say 100MHz, but actually inject to the fpga 80MHz clock?