Hold time violations in simple clock divider

I have fixed this by added an extra register stage to the clock generation output. While I don't believe this changes the functionality or timing of the clock generation at all, it does prevent Quartus from seeing a net that gets routed to a global clock tree as a data input to the Out_Clk flip-flop (even though the input is routed from inside the LE, not from the clock tree). I think this is what was confusing the timing analyzer.

always @(posedge In_Clk, negedge Rst_)
	if (~Rst_)			Staged_Clk	<= 1'b0;
	else 				Staged_Clk	<= ~ Staged_Clk;
always @(posedge In_Clk, negedge Rst_)
	if (~Rst_)			Out_Clk		<= 1'b0;
	else 				Out_Clk		<= Staged_Clk;