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@wcalkins,
making your own clock in this way is not considered good design practice. It is normal that your timing verifier runs into the problems you mention.
Do not use gated or derived clocks to control flip-flops, registers and memories in your design. In case you need a slower or faster clock, use a PLL to make this clock.
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Because this clock has to change frequencies while running, a PLL won't work. According to the Design Recommendations for Altera Devices and the Quartus II Design Assistant (
http://www.altera.com/literature/hb/qts/qts_qii51006.pdf ) on p. 5-8, generating a clock with custom logic is ok, as long as the clock is based on a synchronous source and is not gated. In this case, the Out_Clk signal is routed directly from the output of the register to a CLKCTRL block of the Cyclone III.
Tricky, I would consider this, but in the actual design I am using a counter, not just dividing by 2. This is just the simplest case I could find that shows the problem for diagnostic's sake.
And, as vjAlter mentioned, the registers that use this clock as a source are analyzed properly and meet timing by a wide margin.
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