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Altera_Forum
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15 years ago

Hold time violations and clock distribution

Hello all, I am working on designing a zero-operand stack machine in an Altera FPGA using the Flex EPF10k70Rc240-4 together with a custom memory simulator that includes a variable clock, which ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

@rbugalho:

Thank you SO much. That is exactly what I was looking for--just a way to distribute the off-board clock globally throughout the design in order to eliminate the timing skew caused by distributing that clock as a non-global.

Your suggestion worked, and helped me resolve a week's worth of debugging efforts, so thanks again very much.

One final quick question--when I did route the off-board clock through the LCELL buffer, all the timing warnings went away, but I did get one new warning, coming from Design Assistant:

critical warning: (high) rule a103: design should not contain delay chains. found 1 delay chains.

As far as I can tell, having a delay chain on the global clock shouldn't actually be a problem since the slightly delayed clock will simply be distributed equally throughout the rest of the design, correct? If I'm missing something here, please let me know.

Again, thanks a whole lot for your help.

Robert