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Altera_Forum
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15 years ago

Hold time violations and clock distribution

Hello all, I am working on designing a zero-operand stack machine in an Altera FPGA using the Flex EPF10k70Rc240-4 together with a custom memory simulator that includes a variable clock, which ...
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Altera_Forum
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15 years ago

It looks like your 440KHz is connected to user io and not dedicated clk pin.

Option 1: programming the 25MHz to give 440KHz at source.

option2: keep things same and use 440 signal as clk enable. this requires connecting it to any clk enable in your project(anding) or creating clk enable statement after every edge statement.

option3: divide 25MHz internally to 440 then make the division output global.

accepting global may not be supported in your device. Flex devices are I believe too old and phased out.