Hold time violations and clock distribution

Aha! Thank you, that was quite helpful. I was indeed using the on-board 25 MHz Altera clock to debounce the pushbuttons on the Altera board, which I was using to display debugging information on the FPGA's 7-segment display. I was running the rest of the project on the slower variable clock, which also gives me the option to single-step, which is very helpful for debugging the project.

Now, something strange has come of this. If I put the ENTIRE project on the on-board 25 MHz Altera clock and disable and don't use the off-board variable clock, it compiles without errors. Wonderful! The problem is that I would *really* like to have the project running on the 440 KHz clock for general debugging purposes and so I can single-step through clock cycles.

Now, again, the whole project works when I put it all on the 25 MHz on-board clock. But when I put everything on the 440 KHz clock, I get 2 critical warnings:

critical warning: (high) rule c105: clock signal should be a global signal. (value defined:25). found 1 node(s) related to this rule.

critical warning: node "clock"

and

critical warning: timing requirements for slow timing model timing analysis were not met.

as well as

warning: can't achieve minimum setup and hold requirement clock along 185 path(s). see report window for details.

The only difference here is that I'm port mapping the off-board 440 KHz clock instead of the on-board 25 MHz clock.

It seems, from the first Critical Warning, that it is not recognizing the 440 KHz clock signal (which that warning is referring to) as a global signal and is therefore not distributing it evenly. As I noted in my first message, I tried to set this clock as a "Global Signal" and "Auto Global Clock -> On" in the Assignment Editor, but was given a corresponding error message by Quartus that I couldn't do that:

warning: ignored global signal assignment for i/o pin "clock" because it is user assigned to a non-global pin location.So I'm still confused about why the off-board 440 KHz clock is causing the problems it is, and how to resolve it so that I can use it. It really is very important for debugging purposes.

Thank you VERY much for your help and time so far--I really do appreciate it.

Robert