Hold time violations and clock distribution

oop... 440KHz makes sense and should be dead easy..apologies

If your clk is connected to clock pin then that means it is global and you should not worry about fanout.

Make sure it is not gated inside the logic. It should only be coded as edge at top of every clked process. No other signal should be used for edge triggering as it implies a clk.

You say you got one clk but quartus talks about clk domains

It is likely you have several internal clks , if so either remove them or use need to use small fifos across domains or use clk enable approach