Hold time violations and clock distribution

Thanks very much for the reply! The variable clock is 440 KILOhertz--yeah, my design definitely could not take 440MHz, on an Altera FPGA or otherwise. In fact, the reason I'm using the slower clock and not the 25.125 MHz clock on board the Altera FPGA is to keep speeds slower at first to test the design.

That clock is directly connected from a pin on my connected memory board--I do not use any derived or gated clocks in the design, which is why I'm confused about why the clock signal is being distributed unevenly, and why I (unsuccessfully) tried to specify it as a global signal.

So I'm still perplexed as to why there is such serious clock skew that results in so many hold violations, and why Quartus does not seem to be distributing the clock--which is coming directly from a dedicated pin--evenly to all entities.