Hold time violations and clock distribution

To begin with I doubt you can get 440MHz in any altera device except for tiny logic portions.

FPGA clock rules are well established:

use minimum number of base clocks. All clock inputs must be connected to dedicated clock pins. Use PLLs to make internally derived clocks, if you have to use logic instead(gated clock) then use clock mux and connect it back to global tree. Otherwise do not use gated clocks.

When crossing clock domains use fifo or equivalent logic to transfer data and apply two stage or more synchroniser.

Setup violation is caused by too fast clock while hold violation is caused by clock delay(gated clk).