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hi,
when i tried to make a timing analysis for my design, i get a hold time violation between two nodes.. i attached a screenshot of the error. actually it is not an error, but probably it is the cause of the bad behavior of my design.. i don't have a big knowledge about timing analysis. but i would ask if there are ideas or solutions to eliminate this hold time violation between the indicated nodes..
thank you
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Your clock appears to be generated internally with logic cells. Hold time violations are exactly what you will get in an FPGA when you attempt to use this technique (called 'gated clocks'). The solution is to use the clock input pin as the clock to all; generate clock enable logic inputs rather than using a gated clock.
Kevin Jennings
Honored Contributor
