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NSuku1
New Contributor
New ContributorHLS not generating the VHDL output
Hi, I designed a matrix block using Intel HLS and compiled.. But why does it generate the Verilog output instead of VHDL ? How to make it to generate the VHDL output? Please help me. Thanks, Ni...
Prince_J_IntelNew Contributor
New Contributormy be this link can help to integrate verilog code in vhdl.
https://forums.intel.com/s/question/0D50P00003yyNo0SAE/vhdl-and-verilog-how-i-can-connect-together
