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NSuku1's avatar
NSuku1
Icon for New Contributor rankNew Contributor
7 years ago

HLS not generating the VHDL output

Hi, I designed a matrix block using Intel HLS and compiled.. But why does it generate the Verilog output instead of VHDL ? How to make it to generate the VHDL output? Please help me. Thanks, Ni...
NSuku1's avatar
NSuku1
Icon for New Contributor rankNew Contributor
7 years ago

Oh! NO... I was expecting the hls component will output VHDL and I need to integrate with another component written in VHDL. Now, how can I integrate VHDL with Verilog?

Thanks,

Nivetha

  • HRZ's avatar
    HRZ
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    I integrated a VHDL module inside a Verilog top-module once a few years ago using Xilinx ISE. I would assume it would work the same way when integrating a Verilog module in a VHDL top-module in Quartus: you basically just instantiate the Verilog module in the same way you would instantiate a VHDL module in the top-module and the rest will be handled by the IDE.