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Altera_Forum
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7 years ago

High logic bloat for Platform Designer Interconnect

Hello, I'm a little bit confused about the Avalon MM Interconnect generator in the Platform Designer: I have one EMIF (128b, 233.25 MHz) as Avalon Slave and one Avalon Master (DMA, 128b, same cloc...
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Altera_Forum
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7 years ago

The response FIFO stores responses from a slave to send back to a master. It's always included in a master/slave connection, but it might seem larger with EMIF because the EMIF IP can do bursts, as you mention, but also performs address and data reordering to reduce how often rows in the external memory need to be precharged.