Hi I have this piece of code: in a package i have the record declaration (unconstrained): modelsim is able to compile it, but quartus not (VHDL 2008). I tried 15.1 and 18 version . how can i overcome this without constraint the record in the package?

entity U1 is 	
	generic
	(
		POS_CONFIG_1							: positive := 8;		
		POS_CONFIG_2							: positive := 75;		
		POS_CONFIG_3							: positive := 10;		
		POS_CONFIG_4							: positive := 48;		
		POS_CONFIG_5							: positive := 4		  
	) ;
	port				    																
	( 	
 
	
		IN_REC_DVP_BUS : in DvpBus(data(POS_CONFIG_1-1 downto 0),
											xpos(bwidth(POS_CONFIG_2+POS_CONFIG_3)-1 downto 0),
										       ypos(bwidth(POS_CONFIG_4+POS_CONFIG_5)-1 downto 0));
		
		OUT_REC_DVP_BUS : out DvpBus(data(POS_CONFIG_1-1 downto 0),
									 xpos(bwidth(POS_CONFIG_2+POS_CONFIG_3)-1 downto 0),
									 ypos(bwidth(POS_CONFIG_4+POS_CONFIG_5)-1 downto 0));		
 
		
		CLK_0 		: in std_logic ; 					
		RST_0		: in std_logic 		
	) ;   
end entity U1;
 
 
 
 
type DvpBus is record
   SAMP  		: std_logic;
   VALID		: std_logic;
   DATA 		: std_logic_vector;  
   XPOS	        : unsigned;
   YPOS	        : unsigned;
 
end record DvpBus;
 
 
 
 
 
 
Error (10410): VHDL Type Conversion error at u1.vhd(71): Type Conversion near text or symbol "DvpBus" must have one argument