Hi, I can't get my mod20 sequential circuit to work, the output keeps showing xxxxx. I'm using Quartus ll 8.1 web edition

Hi Joseph,

In JK_flipflop.bdf, the logic gates on the left are overlapping to each other. You have to rearrage the gate so that they are not overlapping.

Warning (275011): Block or symbol "AND3" of instance "inst26" overlaps another block or symbol

Warning (275011): Block or symbol "AND3" of instance "inst28" overlaps another block or symbol

Warning (275011): Block or symbol "AND2" of instance "inst30" overlaps another block or symbol

Warning (275011): Block or symbol "OR2" of instance "inst32" overlaps another block or symbol

Warning (275011): Block or symbol "AND3" of instance "inst34" overlaps another block or symbol

Warning (275011): Block or symbol "AND3" of instance "inst37" overlaps another block or symbol

Warning (275011): Block or symbol "AND2" of instance "inst39" overlaps another block or symbol

Warning (275011): Block or symbol "AND3" of instance "inst42" overlaps another block or symbol

Besides this, I notice that you are instantiating the symbol from Others>maxplus2 which is for another legacy software, Max + PLus II. You have to recreate the design using megafunctions or primitives only. Please note that ModelSim-Intel FPGA edition does not support BDF file for simulation. You may convert the BDF file (after fixing the above error) with the steps provided in my previous reply and simulate using test bench but I would suggest you to design using HDL.

Thanks.

Best regards,

KhaiY