Forum Discussion
sstrell
Super Contributor
6 years agoThe code you've generated from the schematic is Verilog code but your errors are VHDL errors. The compiler is, for some reason, trying to compile this Verilog code as VHDL code.
Do not edit the code at all. It looks like your filename has a .vhd extension instead of .v. Change it to .v since this is Verilog code. Then follow the rest of Khai's instructions.
#iwork4intel
- JHAUG16 years ago
New Contributor
Ok so I changed it to .v but it still gives me errors?