Hi, I can't get my mod20 sequential circuit to work, the output keeps showing xxxxx. I'm using Quartus ll 8.1 web edition

Hi,

I have got a screen full of text now with the following code, now i'm very new to code and if i'mnot mistaken i need to change the quite a lot here becauseit looks nothing like what I expected and when i try to compile I get errors with expected "entity or "architecture" etc. so I have changed where I think it is appropriate however I am still getting the following flow errors, could you advise? thanks again, you've been great help so far. Below i have pasted what i get from what you instructed, is this correct? I'm struggling again, apologies

/ PROGRAM "Quartus Prime"

// VERSION "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition"

// CREATED "Fri Apr 17 14:21:25 2020"

module D_flipflop( <Error (10500): VHDL syntax error at VarilogHDLcodeTrial1.vhd(5) > It asks for"is" then after that asks for "of"

Clock,

Set,

Reset,

LEDA,

LEDB,

LEDC,

LEDD,

LEDE

);

input wire Clock;

input wire Set;

input wire Reset;

output wire LEDA;

output wire LEDB;

output wire LEDC;

output wire LEDD;

output wire LEDE;

wire SYNTHESIZED_WIRE_76;

wire SYNTHESIZED_WIRE_77;

wire SYNTHESIZED_WIRE_78;

wire SYNTHESIZED_WIRE_79;

wire SYNTHESIZED_WIRE_80;

wire SYNTHESIZED_WIRE_81;

wire SYNTHESIZED_WIRE_82;

wire SYNTHESIZED_WIRE_83;

wire SYNTHESIZED_WIRE_84;

wire SYNTHESIZED_WIRE_20;

wire SYNTHESIZED_WIRE_21;

wire SYNTHESIZED_WIRE_22;

wire SYNTHESIZED_WIRE_23;

wire SYNTHESIZED_WIRE_85;

wire SYNTHESIZED_WIRE_54;

wire SYNTHESIZED_WIRE_55;

wire SYNTHESIZED_WIRE_56;

wire SYNTHESIZED_WIRE_57;

wire SYNTHESIZED_WIRE_58;

wire SYNTHESIZED_WIRE_59;

wire SYNTHESIZED_WIRE_60;

wire SYNTHESIZED_WIRE_61;

wire SYNTHESIZED_WIRE_62;

wire SYNTHESIZED_WIRE_63;

wire SYNTHESIZED_WIRE_64;

wire SYNTHESIZED_WIRE_65;

wire SYNTHESIZED_WIRE_66;

wire SYNTHESIZED_WIRE_67;

wire SYNTHESIZED_WIRE_68;

wire SYNTHESIZED_WIRE_69;

wire SYNTHESIZED_WIRE_70;

wire SYNTHESIZED_WIRE_71;

wire SYNTHESIZED_WIRE_72;

wire SYNTHESIZED_WIRE_73;

wire SYNTHESIZED_WIRE_74;

wire SYNTHESIZED_WIRE_75;

assign LEDA = SYNTHESIZED_WIRE_77;

assign LEDB = SYNTHESIZED_WIRE_79;

assign LEDC = SYNTHESIZED_WIRE_81;

assign LEDD = SYNTHESIZED_WIRE_83;

assign LEDE = SYNTHESIZED_WIRE_80;

\7408 b2v_inst(

.3(SYNTHESIZED_WIRE_76),

.2(SYNTHESIZED_WIRE_77),

.1(SYNTHESIZED_WIRE_57));

\7408 b2v_inst1(

.3(SYNTHESIZED_WIRE_78),

.2(SYNTHESIZED_WIRE_79),

.1(SYNTHESIZED_WIRE_59));

entity 7421 b2v_inst10( < Should I be inserting "entity" in here?

.5(SYNTHESIZED_WIRE_80),

.4(SYNTHESIZED_WIRE_81),

.3(SYNTHESIZED_WIRE_76),

.2(SYNTHESIZED_WIRE_82),

.1(SYNTHESIZED_WIRE_72));

\7421 b2v_inst11( < Should I be inserting "entity" in here?

.5(SYNTHESIZED_WIRE_83),

.4(SYNTHESIZED_WIRE_81),

.3(SYNTHESIZED_WIRE_76),

.2(SYNTHESIZED_WIRE_82),

.1(SYNTHESIZED_WIRE_67));

\7421 b2v_inst12(

.5(SYNTHESIZED_WIRE_84),

.4(SYNTHESIZED_WIRE_81),

.3(SYNTHESIZED_WIRE_79),

.2(SYNTHESIZED_WIRE_82),

.1(SYNTHESIZED_WIRE_56));

\7421 b2v_inst13(

.5(SYNTHESIZED_WIRE_80),

.4(SYNTHESIZED_WIRE_83),

.3(SYNTHESIZED_WIRE_81),

.2(SYNTHESIZED_WIRE_76),

.1(SYNTHESIZED_WIRE_58));

\7474 b2v_inst14(

.2D(SYNTHESIZED_WIRE_20),

.2PRN(Set),

.1CLK(Clock),

.1D(SYNTHESIZED_WIRE_21),

.1PRN(Set),

.2CLK(Clock),

.2CLRN(Reset),

.1CLRN(Reset),

.1QN(SYNTHESIZED_WIRE_82),

.2Q(SYNTHESIZED_WIRE_79),

.2QN(SYNTHESIZED_WIRE_76),

.1Q(SYNTHESIZED_WIRE_77));

\7474 b2v_inst15(

.2D(SYNTHESIZED_WIRE_22),

.2PRN(Set),

.1CLK(Clock),

.1D(SYNTHESIZED_WIRE_23),

.1PRN(Set),

.2CLK(Clock),

.2CLRN(Reset),

.1CLRN(Reset),

.1QN(SYNTHESIZED_WIRE_78),

.2Q(SYNTHESIZED_WIRE_83),

.2QN(SYNTHESIZED_WIRE_84),

.1Q(SYNTHESIZED_WIRE_81));

\7408 b2v_inst16(

.3(SYNTHESIZED_WIRE_84),

.2(SYNTHESIZED_WIRE_79),

.1(SYNTHESIZED_WIRE_60));

\7408 b2v_inst2(

.3(SYNTHESIZED_WIRE_78),

.2(SYNTHESIZED_WIRE_77),

.1(SYNTHESIZED_WIRE_55));

\7408 b2v_inst20(

.3(SYNTHESIZED_WIRE_84),

.2(SYNTHESIZED_WIRE_81),

.1(SYNTHESIZED_WIRE_63));

\7408 b2v_inst21(

.3(SYNTHESIZED_WIRE_78),

.2(SYNTHESIZED_WIRE_79),

.1(SYNTHESIZED_WIRE_62));

\7411 b2v_inst22(

.2(SYNTHESIZED_WIRE_78),

.3(SYNTHESIZED_WIRE_83),

.4(SYNTHESIZED_WIRE_80),

.1(SYNTHESIZED_WIRE_61));

\7408 b2v_inst27(

.3(SYNTHESIZED_WIRE_80),

.2(SYNTHESIZED_WIRE_84),

.1(SYNTHESIZED_WIRE_68));

\7408 b2v_inst28(

.3(SYNTHESIZED_WIRE_84),

.2(SYNTHESIZED_WIRE_77),

.1(SYNTHESIZED_WIRE_71));

\7408 b2v_inst29(

.3(SYNTHESIZED_WIRE_85),

.2(SYNTHESIZED_WIRE_83),

.1(SYNTHESIZED_WIRE_69));

\7408 b2v_inst30(

.3(SYNTHESIZED_WIRE_78),

.2(SYNTHESIZED_WIRE_77),

.1(SYNTHESIZED_WIRE_70));

\7408 b2v_inst34(

.3(SYNTHESIZED_WIRE_85),

.2(SYNTHESIZED_WIRE_83),

.1(SYNTHESIZED_WIRE_64));

\7408 b2v_inst35(

.3(SYNTHESIZED_WIRE_85),

.2(SYNTHESIZED_WIRE_76),

.1(SYNTHESIZED_WIRE_65));

\7411 b2v_inst36(

.2(SYNTHESIZED_WIRE_79),

.3(SYNTHESIZED_WIRE_81),

.4(SYNTHESIZED_WIRE_84),

.1(SYNTHESIZED_WIRE_66));

\7421 b2v_inst37(

.5(SYNTHESIZED_WIRE_83),

.4(SYNTHESIZED_WIRE_78),

.3(SYNTHESIZED_WIRE_79),

.2(SYNTHESIZED_WIRE_77),

.1(SYNTHESIZED_WIRE_74));

\7474 b2v_inst40(

.2PRN(Set),

.1CLK(Clock),

.1D(SYNTHESIZED_WIRE_54),

.1PRN(Set),

.1CLRN(Reset),

.1QN(SYNTHESIZED_WIRE_85),

.1Q(SYNTHESIZED_WIRE_80));

assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_55 | SYNTHESIZED_WIRE_56 | SYNTHESIZED_WIRE_57;

assign SYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_58 | SYNTHESIZED_WIRE_59 | SYNTHESIZED_WIRE_60;

assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_61 | SYNTHESIZED_WIRE_62 | SYNTHESIZED_WIRE_63;

assign SYNTHESIZED_WIRE_75 = SYNTHESIZED_WIRE_64 | SYNTHESIZED_WIRE_65 | SYNTHESIZED_WIRE_66 | SYNTHESIZED_WIRE_67;

assign SYNTHESIZED_WIRE_73 = SYNTHESIZED_WIRE_68 | SYNTHESIZED_WIRE_69 | SYNTHESIZED_WIRE_70 | SYNTHESIZED_WIRE_71;

assign SYNTHESIZED_WIRE_22 = SYNTHESIZED_WIRE_72 | SYNTHESIZED_WIRE_73;

assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_74 | SYNTHESIZED_WIRE_75;

endmodule