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Altera_Forum
Honored Contributor
Honored ContributorHelp with Verilog structure
Pardon the simple questions from a Verilog newcomer. I have three modules in a file. Compiles under Quartus OK. Load onto a Max V dev board and only the module designated as "Top" functions. Ch...
Altera_ForumHonored Contributor
Honored ContributorUnless you're building libraries or something it's always best practice to have one module per file and have the file name match the module name. Then, as Tricky said, create a new top-level file that instantiates and interconnects the three sub-modules and declare that as the top-level module in Quartus.
