help with TOP I/O management

You can shift-click to select multiple pins and choose options for how to place them: one by one or in rows or columns. You can also add synthesis attributes to your code for I/O locations, but I don't usually see people doing that because it leaves no room for moving them later in the design process, if necessary. If your board is already fixed, then synthesis attributes may be the way to go.

You cannot turn top-level signal names into pin assignments the way you have mentioned. The only way to do it directly in your code would be with synthesis attributes.

The whole point of the Pin Planner is to make it easy to find valid I/O locations for your design. Not every pin can be used as a GPIO and some pins have special functionality. With the Pin Planner, you can make sure you are using valid pins for your design by perform checks (I/O Assignment Analysis) to make sure that your pin assignments are valid for your selected target device.