help with TOP I/O management

This seems as really nasty, so if I wanted to assign 50 pins I would be manually be grabbing them one by one in pin assignment? Whats even more dreadful to me is, that one has to look in schematics to even get what and where that pin really is.

Can it be declared in top directly? Is there really no way how do declare them?

Maybe I have asked bad question. I have found something called DE10_nano_goldentop. It is funny thing where a possible I/O pins are. Unfortunately this is only for Verilog.

//////////// GPIO_0, GPIO connect to GPIO Default //////////

inout [35:0] GPIO_0,

Is there a way how to get VHDL reference for my board?

How does one in quartus comfirm from VHDL which pin was assigned and where? Let's say we have project where 10 people are working on. If the basement is declared and assigned to PIN only in PIN assigner, then if there one come to a file after some else he/she doesn't know what these pins were used for. For example:

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity TOP is

Port (

x1 : out std_logic; --pwm

reset : in std_logic; -- resets on high

clk : in std_logic

);

Tell me please, as this is a TOP, where does x1 really go ? :) One can assemble it to 10 different pins and each person would do it differently. But if there was a way to assign it like:

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity TOP is

Port (

GPIO_0_D1 : out std_logic; --pwm

reset : in std_logic; -- resets on high

clk : in std_logic

);

then there would be no way someone would assign it somewhere else. Or am I missing something?

sstrell thank you for answer, but could you elaborate it please? What would you do, if possible step_by_step, if you wanted to assign this top to GPIO_0_D1. This would really helped me a lot.