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Altera_Forum's avatar
Altera_Forum
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8 years ago

Help with signed output from ROM

I am new to VHDL and FPGA and have been been trying to generate a sine wave by outputting the data from ROM. The ROM is single port and was generated using IP. The sine wave values were stored in a ....
Altera_Forum's avatar
Altera_Forum
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8 years ago

imho the values are stored e.g. as 16Bit vectors only. Especially as the ROM instantiation ports are "std_logic_vector (width-1 downto 0)". These are just '1' and '0'... whether these are interpreted as signed or unsigned depends on your code and the libraries you are using... If you are using IEEE.std_numeric.all, you declare the vectors as signed and unsigned and thus can "convert" the output of the ROM (std_logic_vector) using "to_signed" function when assigning the ROM Output to the vector.

If you are using std_logic_signed or std_logic_unsigned (Synopsys libraries), you need to "handle" signed or unsigned by yourself, e.g. when applying arithmetics etc.