--- Quote Start ---
The reason you get warnings is to do with the combinatorial process. A cleaner alternative is to use one state, since then all changes are on the clock edge. see code below.
I also now believe my debounce counter of 18 bits is an overkill and I assume 10 bits may be enough. I also added a constant set to 10 for simulation and to 1000 for hardware debounce.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity uppgift_dorr is
port( clk : in std_logic;
reset_n : in std_logic;
key_0, key_1, key_2, key_3 : in std_logic;
LEDR : out std_logic_vector(1 downto 0);
LEDG : out std_logic_vector(1 downto 0)
);
end uppgift_dorr;
architecture Behavioral of uppgift_dorr is
type state_type is (closed,opened,locked,error);
signal State: state_type;
constant max : integer := 10; -- 10 for simulation, 1000 for hardware
signal count_0 : unsigned(9 downto 0) := (others => '0');
signal count_1 : unsigned(9 downto 0) := (others => '0');
signal count_2 : unsigned(9 downto 0) := (others => '0');
signal count_3 : unsigned(9 downto 0) := (others => '0');
signal key_0_d,key_0_final: std_logic;
signal key_1_d,key_1_final: std_logic;
signal key_2_d,key_2_final: std_logic;
signal key_3_d,key_3_final: std_logic;
begin
--debounce
process
begin
wait until clk = '1';
key_0_d <= key_0;
if key_0 = key_0_d then
count_0 <= count_0 +1;
else
count_0 <= (others => '0');
end if;
if count_0 > max then
key_0_final <= key_0;
end if;
key_1_d <= key_1;
if key_1 = key_1_d then
count_1 <= count_1 +1;
else
count_1 <= (others => '0');
end if;
if count_1 > max then
key_1_final <= key_1;
end if;
key_2_d <= key_2;
if key_2 = key_2_d then
count_2 <= count_2 +1;
else
count_2 <= (others => '0');
end if;
if count_2 > max then
key_2_final <= key_2;
end if;
key_3_d <= key_3;
if key_3 = key_3_d then
count_3 <= count_3 +1;
else
count_3 <= (others => '0');
end if;
if count_3 > max then
key_3_final <= key_3;
end if;
end process;
-- Synchronous Process
p0: process(clk, reset_n)
begin
if( reset_n = '0' ) then
State <= opened;
elsif (rising_edge(clk)) then
case State is
when opened =>
LEDG <= "01"; LEDR <= "00";
if ( key_0_final = '0' ) then
State <= closed;
end if;
when closed =>
LEDG <= "10"; LEDR <= "01";
if ( key_1_final = '0') then
State <= opened;
elsif (key_2_final = '0') then
State <= locked;
end if;
when locked =>
LEDG <= "00"; LEDR <= "10";
if ( key_3_final = '0') then
State <= closed;
elsif(key_2_final = '0')then
State <= error;
end if;
when error =>
LEDG <= "11"; LEDR <= "11";
end case;
end if;
end process;
end Behavioral;
--- Quote End ---
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Thanks for all the help Tricky and Kaz. Everything is working prefectly with the Finite state machine now.
Honored Contributor
