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But somehow you have misscopied it (or modified it)
There is an extra "begin" on line 97, and the first debounce process has (clk) as a sensitivity list when it should have no sensitivity list. Otherwise the code is the same.
It also contains extra comments that Kaz's doesnt have either.
I suspect you didnt copy it - you tried to merge it into your own copy.
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Now i deleted my old code and copied kaz's exact code, but i still have inferring latches see below:
what code the problem?
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Jan 02 14:39:19 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uppgift_dorr -c uppgift_dorr
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 2 design units, including 1 entities, in source file uppgift_dorr.vhd
Info (12022): Found design unit 1: uppgift_dorr-Behavioral
Info (12023): Found entity 1: uppgift_dorr
Info (12127): Elaborating entity "uppgift_dorr" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at uppgift_dorr.vhd(103): inferring latch(es) for signal or variable "Next_State", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "Next_State.error" at uppgift_dorr.vhd(103)
Info (10041): Inferred latch for "Next_State.locked" at uppgift_dorr.vhd(103)
Info (10041): Inferred latch for "Next_State.opened" at uppgift_dorr.vhd(103)
Info (10041): Inferred latch for "Next_State.closed" at uppgift_dorr.vhd(103)
Warning (13012): Latch Next_State.opened_380 has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal key_1_final
Warning (13012): Latch Next_State.locked_365 has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal key_1_final
Warning (13012): Latch Next_State.closed_395 has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal Current_State.opened
Warning (13012): Latch Next_State.error_350 has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal key_3_final
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 156 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 6 input pins
Info (21059): Implemented 4 output pins
Info (21061): Implemented 146 logic cells
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 10 warnings
Info: Peak virtual memory: 479 megabytes
Info: Processing ended: Thu Jan 02 14:39:24 2014
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:04
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