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Altera_Forum
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12 years ago

Help with Finite state machine

Hi guys, as an altera pupil i am still struggling with getting FSM to work properly i wonder if it is my testbench that has a problem or the code itself. This is the idea: when key_0 is pressed le...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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use a separate clocked process per each key then in your state machine use sw_0_final,sw_1_final,...etc instead of sw_0,sw_1 ...etc.

declare 3 counters and other signals at top of your design.

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please Kaz, i really do not understand how to go about this as i am a beginner in VHDL. Please do you mind showing me an example with reference to my code above. The 3 counters how is that going to be done and other signals?