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Wow Kaz you are genius, thank you for the help i will try to read about switch debounce logic and see how it can be added to the code, since i am just a beginner in vhdl and using of the Altera DE2-115 hardware. Once more i am grateful
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I am no expert on debouncing logic. some boards have it as part of switch design outside fpga. but you can try this(not tested)
per each switch
signal count_0 : unsigned(17 downto 0) := (others => '0');
signal sw_0_d, sw_0_final : std_logic;
--in a clocked process
sw_0_d <= sw_0;
if sw_0 = sw_0_d then
count_0 <= count_0 +1;
else
count_0 <= (others => '0');
end if;
if count_0 > 250000 then -- about 5 msec bounce time
sw_0_final <= sw_0;
end if;
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