[HELP] VHDL "cant infer register."

The Quartus is detecting an error in my code, the error is this:Error (10821): HDL error at state_machine.vhd(27): can't infer register for "atual" because its behavior does not match any supported register modelI do not know how to solve. I need to use "case" and "type" because my teacher asked.I ask for help to solve. The code is below.Thank you.

--DECLARAÇÃO DE BIBLIOTECAS

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.NUMERIC_STD.ALL;

--DECLARAÇÃO DA ENTIDADE

ENTITY state_machine IS

PORT(

clk,d: IN STD_LOGIC

 );

END ENTITY state_machine;

--DECLARAÇÃO DA ARQUITETURA DA ENTIDADE

ARCHITECTURE behavioral OF state_machine IS

TYPE estado IS(amostrar,naoamostrar);

SIGNAL cancannot: STD_LOGIC;

SIGNAL atual: estado := naoamostrar;

BEGIN

contandoeamostrando: PROCESS(clk,d,atual)

VARIABLE count: INTEGER := 0;

BEGIN

CASE atual IS

WHEN amostrar =>

cancannot <= '1';

IF(RISING_EDGE(clk)) THEN

count := 0;

atual <= naoamostrar;

END IF;

WHEN naoamostrar =>

cancannot <= '0';

IF(RISING_EDGE(clk)) THEN

IF(count<3333333) THEN

count := count + 1;

ELSE

atual <= amostrar;

END IF;

END IF;

END CASE;

END PROCESS;

END ARCHITECTURE;