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Altera_Forum
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8 years ago

Help multiplier vhdl

Hi everyone! I've some problems with a design, I have to Design an algorithmic state machine to implement a parallel series multiplier for eight-bit numbers encoded in SM (Sign-Magnitude). The mul...
Altera_Forum's avatar
Altera_Forum
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8 years ago

That is because + and & operators have equal precedence, so it is doing the add followed by concatenate, giving you a 17 bit result (ie. you code is actaully y := (Y+temp)& "0"; )

You need to put () in to fix the precedence:

y := y + (temp&"0");