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Altera_Forum
Honored Contributor
8 years agoHelp multiplier vhdl
Hi everyone! I've some problems with a design, I have to Design an algorithmic state machine to implement a parallel series multiplier for eight-bit numbers encoded in SM (Sign-Magnitude). The mul...
Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- Sorry but I can´t understand what you want to do. Can you explain me? --- Quote End --- take this example: A = 1111101 B = 1111111 y = 0 count = 0 , A(0) = '1' hence result of A(0) *B = B (1111111), I called it temp update sum: y = y+temp; count <= count + 1; count = 1 , A(1) = '0' hence result of A(1) *B = 0, I called it temp update sum: y = y+temp&'0'; --shift temp by one bit count <= count + 1; count = 2 , A(2) = '1' hence result of A(2) *B = B, I called it temp update sum: y = y+temp&'00'; --shift temp by two bits count <= count + 1; ...