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Honored Contributor
Honored ContributorHelp multiplier vhdl
Hi everyone! I've some problems with a design, I have to Design an algorithmic state machine to implement a parallel series multiplier for eight-bit numbers encoded in SM (Sign-Magnitude). The mul...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- At least you got something... if it was me I will run a 7 states machine (or just a counter 0 to 6). Assuming y = A*B then I might go as below
case count is
when 0 =>
if A(0) = '1' then
temp <= B;
else
temp <= "0000000";
end if;
y <= y + temp; -- first of 7 additions, initialise y to zero
when 1 =>
if A(1) = '1' then
temp <= B;
else
temp <= "0000000";
end if;
y <= y + temp&'0'; --increase weight by one digit
...etc
