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Altera_Forum
Honored Contributor
9 years agohelp in sintax for various inputs to single internal signal vector binary and decimal
hello,,, i have a problem,, i need read 8 inputs from a digital encoder position d1,d2,d3,d4,d5,d6,d7,d8 : in std_logic, each with (0 or 1 state). but my problem is convert these inputs to a si...
Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- Internal_signal <= d8 & d7 & d6 & d5 & d4 & d3 & d2 & d1; this concatenation, and it has no cost on resource. --- Quote End --- Ok thank you and convert this vector of 8 bits to decimal?