Help in my FPGA assignment

Hi Rashed,

Here's what you should have done;

1. Created a design that synthesizes correctly (eg., schematic, VHDL, Verilog)

2. Provide top-level pin assignments that match your hardware.

This is *critical*, you must get the pin assignments correct.

3. Make sure to set unused pins as "input with weak pull-up" (this may be the default, but it depends on what tool version you are using)

4. Re-synthesize the design to use the pin assignments.

5. Read the Quartus warning messages.

You will see one about a missing TimeQuest SDC constraint, but you can ignore that one to start with. However, eventually you will also have to understand how to define timing constraints.

6. Use the Quartus programmer to download the design to your hardware.

What FPGA board do you have? What version of Quartus are you using?

Cheers,

Dave