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Altera_Forum
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12 years ago

Help: how to write a 20ns delay on verilog HDL

how to write a 20ns delay on verilog HDL?

simple example pls

thanks

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Synthesizable: 

    always @ (posedge clk)
data_delayed <= data;

    (clk is 50 MHz)

    Non-synthesizable: 

    `timescale 1ns / 1ps
<module declaration stuff>
always @*
data_delayed =# 20 data;